Sage-Tips

What is Powerplan in VLSI?

Power Plan To connect Power to the Chip by considering issues like EM and IR Drop. Power Routing also called Pre-Routing. Pre-Routing includes creating Power Ring, Stripes/Mesh/Grid, and Standard Cell Power Rails. Power Planning also includes Power Via insertion.

What are the things to be checked before placement stage?

Things to be checked before placement

• Check for any missing / extra placement & routing blockages.
• Don’t use cell list & whether it is properly applied in the tool.
• Don’t touch on cells & nets (make sure that, these are applied)

What is placement in physical design?

Placement is the process of finding a suitable physical location for each cell in the block. Placement does not just place the standard cell available in the synthesized netlist, it also optimized the design. The tool determines the location of each of the standard cell on the core.

Why do we reorder scan chains during placement?

During placement, the optimization may make the scan chain difficult to route due to congestion. Hence the tool will re-order the chain to reduce congestion. This sometimes increases hold time problems in the chain. To overcome these buffers may have to be inserted into the scan path.

What are preplaced cells in physical design?

The critical cells are mostly the cells related to clocks, viz. clock buffers, clock mux, etc. and also few other cells such as RAM’s, ROM,s etc. Since, these cells are placed in to core before placement and routing stage, they are called ‘preplaced cells’.

Why higher metal layers are preferred for VDD and VSS?

Why higher metal layers are preferred for Vdd and Vss? Because it has less resistance and hence leads to less IR drop.

Why are power stripes routed in top metal layers?

Power routes generally conduct a lot of current and due to this IR drop will become into the picture so we are going to higher layers to make these routes less resistive. For power routing top metal layers are preferred because they are thicker and offer less resistance.

Why do you make clock as ideal during floorplan and placement stage?

Make sure to define clocks as ideal in the placement stage, otherwise HFNS will be done on the clock. Clock constraints like skew or clock buffers are not used here and effectively the clock tree will messed up.

What is congestion driven placement?

During congestion driven placement, the cells (Higher cell density) which caused for congestion are spread apart. If the cells along timing critical paths spread apart, the timing constraints along that particular paths are not met which cause for timing violations.

How you will perform cell spreading in placement if congestion is there?

1) If congestion is on/over macro: Check whether the macros are blocking any high density IO pins. If so try to move those macros from that IO pins area. Otherwise, leave enough routing tracks/space for those IO pins and place soft placement blockage over there.