Table of Contents
What is the use of phases in UVM?
UVM Common Phases
| UVM Common Phases | The common phases are the set of function and task phases that all uvm_components execute together. |
|---|---|
| uvm_extract_phase | Extract data from different points of the verficiation environment. |
| uvm_check_phase | Check for any unexpected conditions in the verification environment. |
Can we have user defined phases in UVM?
Creation of user-defined phases in UVM is a possibility although it may hinder in complete re-usability of the testbench. There are chances for components to go out of sync and cause errors related to null pointer handles.
What is the use of final phase in UVM?
The final phase is used to complete any other outstanding actions that the Testbench has not already completed. So these are all the different phases through which a Standard UVM Testbench runs through to generate reset, doing configuration, stimulus generation & performing simulation and finally report generation.
Why connect phase is bottom up in UVM?
Rest other phases are bottom up phases,take the example of connect phase,it is basically used for TLM interconnection between the components and generally its needed to move up the hierarchy as the connections are mostly port to port,port to export and export to export.
Why final phase is top down in UVM?
The final phase is also top down since all the testcases and the stimulus related procedures ends here and it is the final stage before exit. Hence it is being used to check for the final adjustment or loopback is needed or not before exit.
Why is UVM build phase top down?
Typically, build phase contains UVM factory create methods which creates UVM component in testbench. For e.g. Test creates Env, Env creates Agent. In-order to create Driver component, Agent needs to be created first, and Env before that. This is the reason build phase function is top-down.
Why build phase is top down?
What is build_phase in UVM?
Actual simulation that consumes time happens in this UVM phase and runs parallel to other UVM run-time phases. Logically, the first thing to be done is to create testbench component objects so that they can be connected together. This is the reason for the build_phase.
Which callbacks are implemented in UVM_component?
Any class deriving from uvm_component may implement any or all of these callbacks, which are executed in a particular order the run phase is implemented as a task and remaining all are function. 1. Build Phases build phase, connect phase and end_of_elobaration phase belongs to this category.
What are the different phases of UVM testbench simulation?
1. Build Phases build phase, connect phase and end_of_elobaration phase belongs to this category. Phases in this categorize are executed at the start of the UVM testbench simulation, where the testbench components are constructed, configured and testbench components are connected.
How to build a UVM environment?
In order to build the agent, UVM environment is required to be defined and similarly in order to build the environment, the test class has to be defined. Hence, we can only go from top to bottom. To add more flexibility, there are pre and post callbacks to all the runtime phases.