Sage-Tips

What is insertion delay in physical design?

Insertion delay (ID) is a real, measurable delay path through a tree of buffers. Sometimes the clock latency is interpreted as a desired target value for the insertion delay. Clock latency is the time taken by the clock to reach the sink pin from the clock source.

What is source insertion delay?

This refers to the clock delay from the clock origin point, which could be the PLL or maybe the IRC (Internal Reference Clock) to the clock definition point.

Why is insertion delay important?

If by latency you mean insertion delay then OCV has a large impact because the larger the insertion delay the greater the impact on insertion delay of the capture path and thus the greater the impact will be on your setup time.

How can insertion delay be improved?

By adding buffers to the path with least buffers in a launch-capture pair of flops, the difference in the latency/insertion delay for capture and launch (i.e the skew) is reduced. This increases the latency for the flop in whose clock path the buffers were added.

What is CRPR explain?

The delay difference along the common paths of the launching and capturing clock paths is called CRPR.

What is AOCV and POCV in VLSI?

In this article, A comparative study of OCV (On Chip Variation), AOCV (Advance On Chip Variation) and POCV (Parametric On Chip Variation) have been done. Why and how a new variation model has evolved over the previous one and how it is better in term of timing pessimism have also been discussed.

What is OCV and AOCV?

To compensate the variation, static timing analysis(STA) introduces a concept called On Chip Variation(OCV). During design time, extra timing margins are added in timing analysis. OCV has been evolved to Advanced On Chip Variation(AOCV), or even Parametric On Chip Variation(POCV).

What is insertion delay in a clock signal?

The amount of time taken by the clock signal to travel from source to sinks is called the insertion delay. At point A the clock source was there, so clock started building from point A it has to reach the sinks (flops) points B,C,D (flops) . So from point A to point B C D the clock signal has to travel.

What is the difference between latency and insertion delay?

These are typically called insertion delays at this point. (Though some literature does use latency when defining skew as the “difference in best and worst latency”). In short, latency is the value we give the tool before CTS, and insertion delay is the actual value after CTS.

How to reduce the maximum insertion delay of the logic cell?

Maximum insertion delay = setup time + hold time + maximum propagation delay of the logic cell + maximum time of flight ( propagation delay of the interconnect ) 1. Reduce maximum time of flight 2. Reduce propagation delay of logic cell. 3. Reduce critical path in the logic cell

What is the difference between Cell Delay and net delay?

Cell Delay is the amount of delay from input to output of a logic gate in a path. PT calculates the cell delay from delay tables provided in the technology library for the cell. Net Delay Net delay is the amount of delay from the output of a cell to the input of the next cell in a timing path.