Sage-Tips

Why build phase is top down and connect phase is bottom up?

Typically, build phase contains UVM factory create methods which creates UVM component in testbench. For e.g. Test creates Env, Env creates Agent. In-order to create Driver component, Agent needs to be created first, and Env before that. This is the reason build phase function is top-down.

Why UVM Connect phase is bottom up?

Rest other phases are bottom up phases,take the example of connect phase,it is basically used for TLM interconnection between the components and generally its needed to move up the hierarchy as the connections are mostly port to port,port to export and export to export.

Is UVM build phase top down?

All UVM phases are bottom-up except the build phase which is top down (because the parent components have to be constructed already when the child components are built).

Why are there phases in UVM?

The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. That is the main reason why UVM has different phases.

What is top down and bottom-up approach in UVM?

What are the phases in the UVM and explain about the phases which you used mostly in your testbench?

Build Phases build phase, connect phase and end_of_elobaration phase belongs to this category. Phases in this categorize are executed at the start of the UVM testbench simulation, where the testbench components are constructed, configured and testbench components are connected.

What is UVM topology?

The UVM topology task print_topology displays all instantiated components in the environment and helps in debug and to identify if any component got left out. A test sequence object is built and started on the environment virtual sequencer using its start method.

What is UVM verbosity?

The default Verbosity is UVM_MEDIUM. There are different Verbosity level being supported by UVM. These are UVM_NONE, UVM_LOW, UVM_MEDIUM (Default), UVM_HIGH, UVM_FULL, UVM_DEBUG. In case of default Verbosity level i.e. UVM_MEDIUM, any messages with UVM_HIGH or above are filtered out.

What is phasing in UVM?

UVM Phases are a synchronizing mechanism for the environment. Phases are represented by callback methods, A set of predefined phases and corresponding callbacks are provided in uvm_component.

Which phase is bottom-up in UVM?

What are the phases in UVM phasing mechanism?

Build phase and Final phase are the phases in UVM phasing mechanism which are executed in top down fashion and rest all the phases follows the bottom up approach. Lets look at the class hierarchy structure of uvm phasing mechanism first.

Which callbacks are implemented in UVM_component?

Any class deriving from uvm_component may implement any or all of these callbacks, which are executed in a particular order the run phase is implemented as a task and remaining all are function. 1. Build Phases build phase, connect phase and end_of_elobaration phase belongs to this category.

What are the different phases of UVM testbench simulation?

1. Build Phases build phase, connect phase and end_of_elobaration phase belongs to this category. Phases in this categorize are executed at the start of the UVM testbench simulation, where the testbench components are constructed, configured and testbench components are connected.

Is the build phase top down or bottom up?

First I want to correct the question a bit,it’s not only the build phase which is top down but also final phase is there which executes in top down fashion.Lets look at the class hierarchy structure of uvm phasing mechanism first.