Table of Contents
What is a well tap?
Well taps are traditionally used so that your VDD and GND are connected to subtrate and n-wells respectively. This is to help tie them to your VDD and GND levels so that they don’t drift too much (especially…
What is latch-up in physical design?
What is latch-up? A latch-up condition occurs within a design when an unintentional structure, which can be either a thyristor or a silicon-controlled rectifier (SCR) formed through the parasitic elements of the IC, is triggered and becomes locked (latched) into an on state [1].
What is latch-up Prevention in VLSI?
Latch-up prevention techniques: Simply put, latchup prevention/protection includes putting a high resistance in the path so as to limit the current through supply and make β1 *β2 < 1. This can be done with the help of following techniques: Surrounding PMOS and NMOS transistors with an insulating oxide layer (trench).
Why tap cells are used in physical design?
Well tap cells (or Tap cells) are used to prevent the latch-up issue in the CMOS design. Well tap cells connect the nwell to VDD and p-substrate to VSS in order to prevent the latch-up issue.
How well tap prevent latch-up?
What is latch-up How is it prevented?
Latch-up is the low resistance connection between tub and power supply rails. Also to avoid the latch, a separate tap connection is put for each transistor. But this will increase the size of the device so fabs give a minimum space to put a tap, for example, 10 μm in 130 nm technology.
How can I overcome latch-up?
There are several ways to reduce the possibility of latchup:
- Reduce the beta of either or both parasitic devices.
- Increase well and substrate doping concentrations to reduce Rwell and Rsub.
- Provide alternative (or better) collectors of the minority carriers.
Why are well and substrate taps necessary?
taps are traditionally used so that your VDD and GND are connected to subtrate and n-wells respectively. This is to help tie them to your VDD and GND levels so that they don’t drift too much (especially towards the middle of the chip) and cause latchup.